This invention relates to semiconductor memory devices.
More particularly, the present invention relates to an improved conductive line for supplying currents to semiconductor random access memory devices that utilize a magnetic field.
A magnetic memory device has a structure which includes ferromagnetic layers separated by a non-magnetic layer. The ferromagnetic layers have a free magnetic moment vector that can be oriented in one of several preferred directions relative to a pinned magnetic moment vector that is fixed in direction. The orientation of the free magnetic moment vector relative to the pinned magnetic moment vector creates unique resistance states that are used to represent stored information. Accordingly, a detection of changes in resistance allows a magnetic memory device to provide stored information. In typical magnetic memory devices, two resistance states are available. The stored states can be read by passing a sense current through the cell in a sense line because of the difference between the magnetic resistances of the states.
In magnetoresistive random access memory (hereinafter referred to as MRAM) devices, the memory cells are programmed by magnetic fields induced by a single current carrying conductor such as a copper interconnect. Typically, two orthogonal interconnects are employed, with one positioned above (hereinafter referred to as the bit line) the MRAM device and the second positioned below (hereinafter referred to as the digit line) the MRAM device. The purpose of the bit and digit lines is to provide magnetic fields for programming the MRAM device.
However, one of the trends in semiconductor device technology is to scale circuitry to lower power, especially for portable applications, such as laptop computers, cell phones, and pagers. A MRAM device integrates magnetic memory elements and other circuits, for example, a control circuit for magnetic memory elements, comparators for detecting states in a magnetic memory element, input/output circuits, etc. These circuits are usually fabricated in the process of CMOS technology, which operates at low current and high efficiency, in order to lower the power consumption of the MRAM devices.
Thus, it is desirable to fabricate MRAM devices that are more compatible with CMOS technology. However, a problem with MRAM devices is that they typically require large programming currents to write information. Large currents are needed to create a large enough magnetic field to cause the free magnetic moment vector to orientate itself in the desired direction.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide a new and improved interconnect for programming a magnetoresistive random access memory device.
It is an object of the present invention to provide a new and improved interconnect which reduces the power consumption of the device.
It is another object of the present invention to provide a new and improved interconnect which makes the magnetoresistive random access memory device more compatible with CMOS technology.
It is a further object of the present invention to provide a new and improved interconnect which allows the magnetoresistive random access memory device to operate at lower current.
It is another object of the present invention to provide a new and improved interconnect which produces a larger magnetic field for a given programming current.
To achieve the objects and advantages specified above and others, a interconnect for programming a MRAM device is disclosed which includes a metal bit line formed of N metal layers, wherein each N metal layer is separated by an electrically insulating layer, where N is a whole number greater than or equal to two. Further, each N metal layer is connected in series. The purpose of increasing N is to decrease the amount of current needed to induce a given magnetic field for switching the MRAM device. Hence, the current needed to produce a given magnetic field to program the MRAM device is reduced by a factor of N. Thus, the MRAM device can be programmed with less power and, consequently, is more compatible with CMOS technology and portable applications.